5.2.7.33 LCDC Write Protection Status Register
| Name: | LCDC_WPSR |
| Offset: | 0x000000E8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPVSRC[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPVSRC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SEQE | CGD | WPVS | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
| Value | Name |
|---|---|
| 0 | No peripheral internal sequencer error has occurred since the last read of LCDC_WPSR. |
| 1 | A peripheral internal sequencer error has occurred since the last read of LCDC_WPSR. This flag can only be set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
| Value | Description |
|---|---|
| 0 | The clock monitoring circuitry has not been corrupted since the last read of LCDC_WPSR. Under normal operating conditions, this bit is always cleared. |
| 1 | The clock monitoring circuitry has been corrupted since the last read of LCDC_WPSR. This flag can only be set in case of an abnormal clock signal waveform (glitch). |
Bit 0 – WPVS Write Protection Violation Status
| Value | Name |
|---|---|
| 0 | No write protection violation occurred since the last read of LCDC_WPSR. |
| 1 | A write protection violation has occurred since the last read of LCDC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. |