The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name:
LCDC_HEOIER
Offset:
0x00000360
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
CROVF
CRERROR
CREND
Access
W
W
W
Reset
–
–
–
Bit
15
14
13
12
11
10
9
8
CBOVF
CBERROR
CBEND
Access
W
W
W
Reset
–
–
–
Bit
7
6
5
4
3
2
1
0
OVF
ERROR
END
Access
W
W
W
Reset
–
–
–
Bit 18 – CROVF Overflow for Cr Chroma Plane Interrupt
Enable
Bit 17 – CRERROR Bus Transfer Error Detected for Cr Chroma Plane
Interrupt Enable
Bit 16 – CREND End of Frame DMA for Cr Chroma Plane Transfer
Interrupt Enable
Bit 10 – CBOVF Overflow for Cb or CbCr Chroma Plane Interrupt
Enable
Bit 9 – CBERROR Bus Transfer Error Detected for Cb or CbCr Chroma
Plane Interrupt Enable
Bit 8 – CBEND End of Frame DMA Transfer for Cb or CbCr Chroma
Plane Interrupt Enable
Bit 2 – OVF Overflow Interrupt
Enable
Bit 1 – ERROR Bus Transfer Error Detected Interrupt
Enable
Bit 0 – END End of Frame DMA Transfer Interrupt
Enable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
