5.2.7.37 Overlay 1 Interrupt Status Register
| Name: | LCDC_OVR1ISR |
| Offset: | 0x0000016C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | ERROR | END | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – OVF Overflow Detected
| Value | Description |
|---|---|
| 0 | No overflow occurred since last read of LCDC_OVR1ISR. |
| 1 | An overflow occurred, at least one DMA transfer is still running at the End Of Frame. This flag is reset after a read operation |
Bit 1 – ERROR Bus Error Detected
| Value | Description |
|---|---|
| 0 | No system bus error has been detected since the last read of LCDC_OVR1ISR. |
| 1 | A system bus error has been detected. This flag is reset after a read operation |
Bit 0 – END End of Frame DMA Transfer
| Value | Description |
|---|---|
| 0 | No end of transfer has been detected since last read of LCDC_OVR1ISR. |
| 1 | End of transfer has been detected. This flag is reset after a read operation. |