5.2.7.20 Base Layer Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt source is disabled.

1: The corresponding interrupt source is enabled.

Name: LCDC_BASEIMR
Offset: 0x00000068
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      OVFERROREND 
Access RRR 
Reset 000 

Bit 2 – OVF Overflow Interrupt Mask

Bit 1 – ERROR Transfer Error Interrupt Mask

Bit 0 – END End of Frame DMA Transfer Interrupt Mask