5.2.7.17 LCDC Attribute Status Register

Name: LCDC_ATTRS
Offset: 0x00000040
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 SIP        
Access R 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HEOCLOVR2CLOVR1CLBASECL 
Access RRRR 
Reset 0000 
Bit 76543210 
     HEOOVR2OVR1BASE 
Access RRRR 
Reset 0000 

Bit 31 – SIP Synchronization In Progress

ValueDescription
0

Clock domain synchronization is terminated.

1

Synchronization is in progress. Access to LCDC_ATTRE has no effect.

Bit 11 – HEOCL High-End Overlay Color Table Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the High-end Overlay CLUT.

Bit 10 – OVR2CL Overlay 2 Color Table Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the Overlay 2 CLUT.

Bit 9 – OVR1CL Overlay 1 Color Table Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the Overlay 1 CLUT.

Bit 8 – BASECL Base Layer Color Table Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the base CLUT.

Bit 3 – HEO High-End Overlay Update Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for High-end Overlay.

Bit 2 – OVR2 Overlay 2 Update Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the Overlay 2 layer.

Bit 1 – OVR1 Overlay 1 Update Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the Overlay 1 layer.

Bit 0 – BASE Base Layer Update Status

ValueDescription
0

No effect.

1

Indicates that an update request is pending for the base layer.