5.2.7.14 LCDC Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

Name: LCDC_LCDIMR
Offset: 0x00000034
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 WPIM        
Access R 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HEOIMOVR2IMOVR1IMBASEIM 
Access RRRR 
Reset 0000 
Bit 76543210 
    FIFOERRIMROWIMDISPIMDISIMSOFIM 
Access RRRRR 
Reset 00000 

Bit 31 – WPIM Write Protection Interrupt Mask

Bit 11 – HEOIM High-End Overlay Interrupt Mask

Bit 10 – OVR2IM Overlay 2 Interrupt Mask

Bit 9 – OVR1IM Overlay 1 Interrupt Mask

Bit 8 – BASEIM Base Layer Interrupt Mask

Bit 4 – FIFOERRIM Output FIFO Error Interrupt Mask

Bit 3 – ROWIM Row Interrupt Mask

Bit 2 – DISPIM Power-up/Power-down Sequence Terminated Interrupt Mask

Bit 1 – DISIM LCD Disable Interrupt Mask

Bit 0 – SOFIM Start of Frame Interrupt Mask