5.2.7.59 Overlay 2 Configuration Register 1
This register can only be written if O2WPCFGE is cleared in the LCDC Write Protection Mode Register.
| Name: | LCDC_OVR2CFG1 |
| Offset: | 0x00000280 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLUTMODE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RGBMODE[3:0] | GAM | CLUTEN | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 9:8 – CLUTMODE[1:0] CLUT Mode Input Selection
| Value | Name | Description |
|---|---|---|
| 0 | CLUT_1BPP |
CLUT mode set to 1 bit per pixel |
| 1 | CLUT_2BPP |
CLUT mode set to 2 bits per pixel |
| 2 | CLUT_4BPP |
CLUT mode set to 4 bits per pixel |
| 3 | CLUT_8BPP |
CLUT mode set to 8 bits per pixel |
Bits 7:4 – RGBMODE[3:0] RGB Mode Input Selection
| Value | Name | Description |
|---|---|---|
| 0 | 12BPP_RGB_444 |
12 bpp RGB 444 |
| 1 | 16BPP_ARGB_4444 |
16 bpp ARGB 4444 |
| 2 | 16BPP_RGBA_4444 |
16 bpp RGBA 4444 |
| 3 | 16BPP_RGB_565 |
16 bpp RGB 565 |
| 4 | 16BPP_ARGB_1555 |
16 bpp ARGB 1555 |
| 5 | 18BPP_RGB_666 |
18 bpp RGB 666 |
| 6 | 18BPP_RGB_666PACKED |
18 bpp RGB 666 PACKED |
| 7 | 19BPP_ARGB_1666 |
19 bpp ARGB 1666 |
| 8 | 19BPP_ARGB_PACKED |
19 bpp ARGB 1666 PACKED |
| 9 | 24BPP_RGB_888 |
24 bpp RGB 888 |
| 10 | 24BPP_RGB_888_PACKED |
24 bpp RGB 888 PACKED |
| 11 | 25BPP_ARGB_1888 |
25 bpp ARGB 1888 |
| 12 | 32BPP_ARGB_8888 |
32 bpp ARGB 8888 |
| 13 | 32BPP_RGBA_8888 |
32 bpp RGBA 8888 |
Bit 2 – GAM Gamma Correction
| Value | Description |
|---|---|
| 0 |
Gamma correction is disabled |
| 1 |
Gamma correction is enabled |
Bit 0 – CLUTEN CLUT Mode Enable
| Value | Description |
|---|---|
| 0 |
RGB mode is selected. |
| 1 |
CLUT mode is selected. |