5.2.7.13 LCDC Interrupt Disable Register

This register can only be written if WPITE is cleared in the LCDC_WPMR.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: LCDC_LCDIDR
Offset: 0x00000030
Reset: 
Property: Write-only

Bit 3130292827262524 
 WPID        
Access W 
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HEOIDOVR2IDOVR1IDBASEID 
Access WWWW 
Reset  
Bit 76543210 
    FIFOERRIDROWIDDISPIDDISIDSOFID 
Access WWWWW 
Reset  

Bit 31 – WPID Write Protection Interrupt Disable

Bit 11 – HEOID High-End Overlay Interrupt Disable

Bit 10 – OVR2ID Overlay 2 Interrupt Disable

Bit 9 – OVR1ID Overlay 1 Interrupt Disable

Bit 8 – BASEID Base Layer Interrupt Disable

Bit 4 – FIFOERRID Output FIFO Error Interrupt Disable

Bit 3 – ROWID Row Interrupt Disable

Bit 2 – DISPID Power-up/Power-down Sequence Terminated Interrupt Disable

Bit 1 – DISID LCD Disable Interrupt Disable

Bit 0 – SOFID Start of Frame Interrupt Disable