5.2.7.8 LCDC Configuration Register 7
This register can only be written if WPCFGE is cleared in the LCDC Write Protection Mode Register.
GCLK must be running before writing in this register.| Name: | LCDC_LCDCFG7 |
| Offset: | 0x0000001C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ROW[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ROW[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 10:0 – ROW[10:0] Row Identifier For Row Interrupt Signal
When the LCDC timing engine row pointer reaches the field ROW, an interrupt is triggered.
Indicates a line in reverse order, i.e., ROW0 is the last line and ROW height-1 the first line displayed.