5.2.7.1 LCDC Configuration Register 0
This register can only be written if WPCFGE is cleared in the LCDC Write Protection Mode Register.
GCLK must be running before writing in this register.
| Name: | LCDC_LCDCFG0 |
| Offset: | 0x00000000 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKPWMSEL | CLKBYP | CLKPOL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bits 23:16 – CLKDIV[7:0] LCDC Clock Divider
8-bit width clock divider for pixel clock (LCDC_PCK). If CLKBYP = 0, the pixel clock frequency formula is:
LCDC_PCK_freq = GCLK_freq / (CLKDIV+2)
Bit 3 – CLKPWMSEL LCDC PWM Clock Source Selection
| Value | Description |
|---|---|
| 0 | The slow clock is selected and feeds the PWM module. |
| 1 | The peripheral clock (MCK) is selected and feeds the PWM module. |
Bit 1 – CLKBYP LCDC Pixel Clock Divider Bypass
| Value | Description |
|---|---|
| 0 | Pixel clock divider is not bypassed. LCDC_PCK is defined with CLKDIV parameter. |
| 1 | Pixel clock divider is bypassed. LCDC_PCK = GCLK clock |
Bit 0 – CLKPOL LCDC Clock Polarity
| Value | Description |
|---|---|
| 0 | Data/Control signals are launched on the rising edge of the pixel clock. |
| 1 | Data/Control signals are launched on the falling edge of the pixel clock. |