5.2.7.29 Base Layer Configuration Register 4
This register can only be written if BWPCFGE is cleared in the LCDC Write Protection Mode Register.
| Name: | LCDC_BASECFG4 |
| Offset: | 0x0000008C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DISCEN | REP | DMA | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 4 – DISCEN Discard Area Enable
| Value | Description |
|---|---|
| 0 | The whole frame is retrieved from memory. |
| 1 | The DMA channel discards the area located at screen coordinates {DISCXPOS, DISCYPOS}. |
Bit 1 – REP Use Replication Logic to Expand RGB Color to 24 Bits
In all ARGB formats with one transparency bit, REP affects the A field interpretation when A=1. If REP=0, then A=1 will be interpreted as Alpha = 0x80 (half transparent). If REP=1, then A=1 will be interpreted as Alpha = 0xFF (full opaque)
| Value | Description |
|---|---|
| 0 | When the selected pixel depth is less than 24 bpp, the pixel is shifted and LSBs are set to 0. |
| 1 | When the selected pixel depth is less than 24 bpp, the pixel is shifted and the LSB replicates the MSB. |
Bit 0 – DMA Use DMA Data Path
| Value | Description |
|---|---|
| 0 | The default color is used on the base layer. |
| 1 | The DMA channel retrieves the pixel stream from the memory. |