5.2.7.117 Overlay 1 CLUT Register x
Note:
- The reset value is undefined because the CLUT registers are located in the embedded RAM.
- OVR1CFG1.CLUTEN and OVR1CFG1.GAM must be disabled in order to read/write in the CLUT through the User Interface.
| Name: | LCDC_OVR1CLUTx |
| Offset: | 0x0B00 + x*0x04 [x=0..255] |
| Reset: | 0x– |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ACLUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RCLUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GCLUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BCLUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | – | – | – | – | |
Bits 31:24 – ACLUT[7:0] Alpha Color Entry
Indicates the 8-bit width Alpha component of the CLUT.
Bits 23:16 – RCLUT[7:0] Red Color Entry
Indicates the 8-bit width red color of the CLUT.
Bits 15:8 – GCLUT[7:0] Green Color Entry
Indicates the 8-bit width green color of the CLUT.
Bits 7:0 – BCLUT[7:0] Blue Color Entry
Indicates the 8-bit width blue color of the CLUT.