The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Name:
LCDC_HEOIMR
Offset:
0x00000368
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
CROVF
CRERROR
CREND
Access
R
R
R
Reset
0
0
0
Bit
15
14
13
12
11
10
9
8
CBOVF
CBERROR
CBEND
Access
R
R
R
Reset
0
0
0
Bit
7
6
5
4
3
2
1
0
OVF
ERROR
END
Access
R
R
R
Reset
0
0
0
Bit 18 – CROVF Overflow for Cr Chroma Plane Interrupt Mask
Bit 17 – CRERROR Bus Transfer Error Detected for Cr Chroma Plane Interrupt Mask
Bit 16 – CREND End of Frame DMA Transfer for Cr Chroma Plane Interrupt Mask
Bit 10 – CBOVF Overflow for Cb or CbCr Chroma Plane Interrupt Mask
Bit 9 – CBERROR Bus Transfer Error Detected for Cb or CbCr Chroma Plane Interrupt Mask
Bit 8 – CBEND End of Frame DMA Transfer for Cb or CbCr Chroma
Plane Interrupt Mask
Bit 2 – OVF Overflow Interrupt Mask
Bit 1 – ERROR Bus Transfer Error Detected Interrupt
Mask
Bit 0 – END End of Frame DMA Transfer Interrupt
Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
