5.2.7.11 LCDC Status Register

Name: LCDC_LCDSR
Offset: 0x00000028
Reset: 0x00000020
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  CMSTSSDSTSSIPSTSPWMSTSDISPSTSLCDSTSCLKSTS 
Access RRRRRRR 
Reset 0100000 

Bit 6 – CMSTS Color Mode Signal Status

ValueDescription
0

Color mode signal output is zero.

1

Color mode signal output is one.

Bit 5 – SDSTS Shutdown Signal Status

ValueDescription
0

Shutdown signal output is zero.

1

Shutdown signal output is one.

Bit 4 – SIPSTS Synchronization In Progress

ValueDescription
0

Clock domain synchronization is terminated.

1

Synchronization is in progress. Access to the registers LCDC_LCDCCFG[0..7], LCDC_LCDEN and LCDC_LCDDIS has no effect.

Bit 3 – PWMSTS LCDC PWM Signal Status

ValueDescription
0

PWM is disabled.

1

PWM signal is activated.

Bit 2 – DISPSTS LCDC DISP Signal Status

ValueDescription
0

DISP is disabled.

1

DISP signal is activated.

Bit 1 – LCDSTS LCDC Synchronization Status

ValueDescription
0

Timing engine is disabled.

1

Timing engine is running.

Bit 0 – CLKSTS Clock Status

ValueDescription
0

Pixel clock is disabled.

1

Pixel clock is running.