5.2.7.6 LCDC Configuration Register 5
This register can only be written if WPCFGE is cleared in the LCDC Write Protection Mode Register.
GCLK must be running before writing in this register.| Name: | LCDC_LCDCFG5 |
| Offset: | 0x00000014 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GUARDTIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VSPHO | VSPSU | DPI | MODE[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DISPDLY | DITHER | DISPPOL | VSPDLYE | VSPDLYS | VSPOL | HSPOL | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:16 – GUARDTIME[7:0] LCD Display Guard Time
Number of frames inserted during start-up before LCDC_DISP signal is enabled, and after LCDC_DISP signal is disabled.
Bit 13 – VSPHO LCDC Vertical Synchronization Pulse Hold Configuration
| Value | Description |
|---|---|
| 0 | The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. |
| 1 | The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. |
Bit 12 – VSPSU LCDC Vertical Synchronization Pulse Setup Configuration
| Value | Description |
|---|---|
| 0 | The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. |
| 1 | The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. |
Bit 11 – DPI Display Pixel Interface Compatible Mode
| Value | Description |
|---|---|
| 0 | Legacy pixel mapping. |
| 1 | Activates the DPI compliant pixel stream. See field MODE: LCDC Output Mode. |
Bits 10:8 – MODE[2:0] LCDC Output Mode
When DPI = 0:
| Value | Name | Description |
|---|---|---|
| 0 | OUTPUT_12BPP | LCD Output mode is set to 12 bits per pixel |
| 1 | OUTPUT_16BPP | LCD Output mode is set to 16 bits per pixel |
| 2 | OUTPUT_18BPP | LCD Output mode is set to 18 bits per pixel |
| 3 | OUTPUT_24BPP | LCD Output mode is set to 24 bits per pixel |
When DPI = 1:
| Value | Name | Description |
|---|---|---|
| 0 | OUTPUT_DPI_16BPPCFG1 | LCD Output mode is set to 16 bits per pixel Configuration 1 |
| 1 | OUTPUT_DPI_16BPPCFG2 | LCD Output mode is set to 1 bits per pixel Configuration 2 |
| 2 | OUTPUT_DPI_16BPPCFG3 | LCD Output mode is set to 16 bits per pixel Configuration 3 |
| 3 | OUTPUT_DPI_18BPPCFG1 | LCD Output mode is set to 18 bits per pixel Configuration 1 |
| 4 | OUTPUT_DPI_18BPPCFG2 | LCD Output mode is set to 18 bits per pixel Configuration 2 |
| 5 | OUTPUT_DPI_24BPP | LCD Output mode is set to 24 bits per pixel |
Bit 7 – DISPDLY LCDC Display Power Signal Synchronization
| Value | Description |
|---|---|
| 0 | The LCDC_DISP signal is asserted synchronously with the second active edge of the horizontal pulse. |
| 1 | The LCDC_DISP signal is asserted asynchronously with both edges of the horizontal pulse. |
Bit 6 – DITHER LCDC Dithering
| Value | Description |
|---|---|
| 0 | Dithering logical unit is disabled. |
| 1 | Dithering logical unit is activated. |
Bit 4 – DISPPOL Display Signal Polarity
| Value | Description |
|---|---|
| 0 | Active high. |
| 1 | Active low. |
Bit 3 – VSPDLYE Vertical Synchronization Pulse End
| Value | Description |
|---|---|
| 0 | The second active edge of the vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. |
| 1 | The second active edge of the vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. |
Bit 2 – VSPDLYS Vertical Synchronization Pulse Start
| Value | Description |
|---|---|
| 0 | The first active edge of the vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. |
| 1 | The first active edge of the vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. |
Bit 1 – VSPOL Vertical Synchronization Pulse Polarity
| Value | Description |
|---|---|
| 0 | Active high. |
| 1 | Active low. |
Bit 0 – HSPOL Horizontal Synchronization Pulse Polarity
| Value | Description |
|---|---|
| 0 | Active high. |
| 1 | Active low. |