5.2.7.108 High-End Overlay Configuration Register 28

This register can only be written if HEWPCFGE is cleared in the LCDC Write Protection Mode Register.

Name: LCDC_HEOCFG28
Offset: 0x00000400
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
     VXSCOFF1[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
     VXSCOFF[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
     VXSYOFF1[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
     VXSYOFF[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 27:24 – VXSCOFF1[3:0] Vertical Scaler Chroma Default Phase for Field 1

Bits 19:16 – VXSCOFF[3:0] Vertical Scaler Chroma Default Phase for Field 0 or Progressive Scan

Bits 11:8 – VXSYOFF1[3:0] Vertical Scaler Luma Default Phase for Field 1

Bits 3:0 – VXSYOFF[3:0] Vertical Scaler Luma Default Phase for Field 0 or Progressive Scan