5.2.7.80 High-End Overlay Configuration Register 0
This register can only be written if HEWPCFGE is cleared in the LCDC Write Protection Mode Register.
| Name: | LCDC_HEOCFG0 |
| Offset: | 0x00000390 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BLENCC[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BLEN[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 10:8 – BLENCC[2:0] System Bus Burst Length for Cb-Cr Channel
| Value | Name | Description |
|---|---|---|
| 0 | INCR1 |
System bus access is started as soon as there is enough space in the FIFO to store one data. |
| 1 | INCR4 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. A system bus INCR4 Burst is used by default. INCR1 is used for bursts less than 4. |
| 2 | INCR8 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. A system bus INCR8 Burst is used by default. INCR4 bursts are used for bursts of 4 beats. INCR1 is used for bursts less than 4. |
| 3 | INCR16 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. A system bus INCR16 Burst is used by default. INCR8 and INCR4 bursts are respectively used for bursts of 8 and 4 beats. INCR1 is used for bursts less than 4. |
| 4 | INCR32 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 32 data. A system bus INCR32 Burst is used by default. INCR16, INCR8 and INCR4 bursts are respectively used for bursts of 16, 8 and 4 beats. INCR1 is used for bursts less than 4. |
Bits 6:4 – BLEN[2:0] System Bus Burst Length
| Value | Name | Description |
|---|---|---|
| 0 | INCR1 |
System bus access is started as soon as there is enough space in the FIFO to store one data. |
| 1 | INCR4 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. A system bus INCR4 Burst is used by default. INCR1 is used for bursts less than 4. |
| 2 | INCR8 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. A system bus INCR8 Burst is used by default. INCR4 bursts are used for bursts of 4 beats. INCR1 is used for bursts less than 4. |
| 3 | INCR16 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. A system bus INCR16 Burst is used by default. INCR8 and INCR4 bursts are respectively used for bursts of 8 and 4 beats. INCR1 is used for bursts less than 4. |
| 4 | INCR32 |
System bus access is started as soon as there is enough space in the FIFO to store a total amount of 32 data. A system bus INCR32 Burst is used by default. INCR16, INCR8 and INCR4 bursts are respectively used for bursts of 16, 8 and 4 beats. INCR1 is used for bursts less than 4. |