5.2.7.35 Overlay 1 Interrupt Disable Register

This register can only be written if O1WPITE is cleared in the LCDC Write Protection Mode Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: LCDC_OVR1IDR
Offset: 0x00000164
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      OVFERROREND 
Access WWW 
Reset  

Bit 2 – OVF Overflow Interrupt Disable

Bit 1 – ERROR Error Interrupt Disable

Bit 0 – END End of Frame DMA Transfer Interrupt Disable