5.2.7.3 LCDC Configuration Register 2
This register can only be written if WPCFGE is cleared in the LCDC Write Protection Mode Register.
GCLK must be running before writing in this register.
| Name: | LCDC_LCDCFG2 |
| Offset: | 0x00000008 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VBPW[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VBPW[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VFPW[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VFPW[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 25:16 – VBPW[9:0] Vertical Back Porch Width
Indicates the number of lines at the beginning of the frame. The blanking interval is equal to (VBPW+1) lines.
Bits 9:0 – VFPW[9:0] Vertical Front Porch Width
Indicates the number of lines at the end of the frame. The blanking interval is equal to (VFPW+1) lines.