14.4.25 CAN 1 FIFO x Status Register

Note:
  1. The individual bytes in this multibyte register can be accessed with the following register names:
    • CxFIFOSTAyT: Accesses the top byte FIFOSTAy[31:24].
    • CxFIFOSTAyU: Accesses the upper byte FIFOSTAy[23:16].
    • CxFIFOSTAy: Accesses the byte FIFOSTAy[31:0].
  2. [x] denotes FIFO number, from 1 to 7.
  3. FIFOCI[4:0] gives a zero-indexed value to the message in the FIFO. If the FIFO is four message deep (FSIZE = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO.
  4. This bit is updated when a message completes (or aborts) or when the FIFO is reset.
  5. This bit is reset on any read of this register or when the TXQ is reset.
Name: C1FIFOSTAx
Offset: 0x2660, 0x266C, 0x2678, 0x2684, 0x2690, 0x269C, 0x26A8

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    FIFOCI[4:0] 
Access [R[R[R[R[R 
Reset 00000 
Bit 76543210 
 TXABTTXLARBTXERRTXATIFRXOVIFTFERFFIFTFHRFHIFTFNRFNIF 
Access RRRHS/CHS/CRRR 
Reset 00000000 

Bits 12:8 – FIFOCI[4:0]  FIFO Message Index bits(3)

NameDescription
TXEN = 1 (FIFO configured as a transmit buffer) A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0 (FIFO configured as a receive buffer) A read of this register will return an index to the message that the FIFO will use to save the next message.

Bit 7 – TXABT  Message Aborted Status bit(5)

ValueDescription
1 Message was aborted.
0 Message completed successfully.

Bit 6 – TXLARB  Message Lost Arbitration Status bit(4)

ValueDescription
1 Message lost arbitration while being sent.
0 Message did not lose arbitration while being sent.

Bit 5 – TXERR  Error Detected During Transmission bit(4)

ValueDescription
1 A bus error occurred while the message was being sent.
0 A bus error did not occur while the message was being sent.

Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending bit

ValueNameDescription
1 TXEN = 1 (FIFO configured as a transmit buffer) Interrupt is pending.
0 TXEN = 1 (FIFO configured as a transmit buffer) Interrupt is not pending.
x TXEN = 0 (FIFO configured as a receive buffer) Unused, reads as ‘0’.

Bit 3 – RXOVIF Receive FIFO Overflow Interrupt Flag bit

ValueNameDescription
x TXEN = 1 (FIFO configured as a transmit buffer) Unused, reads as ‘0’.
1 TXEN = 0 (FIFO configured as a receive buffer) Overflow event has occurred.
0 TXEN = 0 (FIFO configured as a receive buffer) No overflow event occurred.

Bit 2 – TFERFFIF Transmit/Receive FIFO Empty/Full Interrupt Flag bit

ValueNameDescription
1 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is empty.
0 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is not empty, at least one message is queued to be transmitted.
1 TXEN = 0 (FIFO configured as a receive buffer) FIFO is full.
0 TXEN = 0 (FIFO configured as a receive buffer) FIFO is not full.

Bit 1 – TFHRFHIF Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag bit

ValueNameDescription
1 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is less than or equal to half-full.
0 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is greater than half-full
1 TXEN = 0 (FIFO configured as a receive buffer) FIFO is greater than or equal to half-full
0 TXEN = 0 (FIFO configured as a receive buffer) FIFO is less than half-full

Bit 0 – TFNRFNIF Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag bit

ValueNameDescription
1 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is not full.
0 TXEN = 1 (FIFO configured as a transmit buffer) FIFO is full.
1 TXEN = 0 (FIFO configured as a receive buffer) FIFO is not empty, has at least one message.
0 TXEN = 0 (FIFO configured as a receive buffer) FIFO is empty.