14.4.7 CAN Interrupt Code Register
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxVECT: Accesses the top byte VEC[31:24].
- CxVECU: Accesses the upper byte VEC[23:16].
- CxVECH: Accesses the byte VEC[31:0].
| Name: | CxVEC |
| Offset: | 0x2618, 0x2908 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXCODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXCODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FILHIT[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ICODE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 30:24 – RXCODE[6:0] Receive Interrupt Flag Code bits
| Value | Description |
|---|---|
| 1111111-1000001 | Reserved |
| 1000000 | No interrupt |
| 0111111-0000100 | Reserved |
| 0000011 | FIFO 3 interrupt (RFIF[3] is set) |
| 0000010 | FIFO 2 interrupt (RFIF[2] is set) |
| 0000001 | FIFO 1 interrupt (RFIF[1] is set) |
| 0000000 | Reserved; FIFO 0 cannot receive. |
Bits 22:16 – TXCODE[6:0] Transmit Interrupt Flag Code bits
| Value | Description |
|---|---|
| 1111111-1000001 | Reserved |
| 1000000 | No interrupt |
| 0111111-0000100 | Reserved |
| 0000011 | FIFO 3 interrupt (TFIF[3] is set) |
| 0000010 | FIFO 2 interrupt (TFIF[2] is set) |
| 0000001 | FIFO 1 interrupt (TFIF[1] is set) |
| 0000000 | FIFO 0 interrupt (TFIF[0] is set) |
Bits 12:8 – FILHIT[4:0] Filter Hit Number bits
| Value | Description |
|---|---|
| 11111 | Filter 31 |
| 11110 | Filter 30 |
| ... | |
| 00001 | Filter 1 |
| 00000 | Filter 0 |
Bits 6:0 – ICODE[6:0] Interrupt Flag Code bits
| Value | Description |
|---|---|
| 1111111-1001011 | Reserved |
| 1001010 | Transmit attempt interrupt (any bit in CxTXATIF is set) |
| 1001001 | Transmit event FIFO interrupt (any bit in CxTEFSTA is set) |
| 1001000 | Invalid message occurred (IVMIF/IE). |
| 1000111 | CAN module mode change occurred (MODIF/IE). |
| 1000110 | CAN timer overflow (TBCIF/IE) |
| 1000101 | RX/TX MAB overflow/underflow (RX: Message received before previous message was saved to memory; TX: Cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE) |
| 1000100 | Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE) |
| 1000011 | Receive FIFO overflow interrupt (any bit in CxRXOVIF is set). |
| 1000010 | Wake-up interrupt (WAKIF/WAKIE) |
| 1000001 | Error interrupt (CERRIF/IE) |
| 1000000 | No interrupt |
| 0111111-0100000 | Reserved |
| 0011111 | FIFO 31 Interrupt (TFIF[31] or RFIF[31] set) |
| ... | |
| 0000001 | FIFO 1 Interrupt (TFIF1 or RFIF1 is set) |
| 0000000 | FIFO 0 Interrupt (TFIF0 is set) |