14.4.11 CAN Receive Overflow Interrupt Status Register
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxRXOVIFT: Accesses the top byte RXOVIF[31:24].
- CxRXOVIFU: Accesses the upper byte RXOVIF[23:16].
- CxRXOVIF: Accesses the byte RXOVIF[15:8].
- RFOVIFx mirrors the overflow bit of its respective FIFO register, individual flags need to be cleared in said FIFO register.
| Name: | CxRXOVIF |
| Offset: | 0x2628, 0x2918 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RFOVIF[30:23] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RFOVIF[22:15] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RFOVIF[14:7] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RFOVIF[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 31:1 – RFOVIF[30:0] Receive FIFO Overflow Interrupt Pending bits
| Value | Description |
|---|---|
| 1 | Interrupt is pending. |
| 0 | Interrupt is not pending. |