14.4.10 CAN Transmit Interrupt Status Register
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxTXIFT: Accesses the top byte TXIF[31:24]
- CxTXIFU: Accesses the upper byte TXIF[23:16]
- CxTXIF: Accesses the byte TXIF[31:0]
- TFIFx is the ‘or’ of all enabled TX FIFO flags (individual flags need to be cleared in the FIFO register).
| Name: | CxTXIF |
| Offset: | 0x2624, 0x2914 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TFIF[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TFIF[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TFIF[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TFIF[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – TFIF[31:0] Transmit FIFO/TXQ Interrupt Pending bits
| Value | Description |
|---|---|
| 1 | One or more enabled transmit FIFO/TXQ interrupts are pending for the respective FIFO/TXQ. |
| 0 | No enabled transmit FIFO/TXQ interrupts for the respective FIFO/TXQ are pending. |