14.4.1 CAN FD x Control Register

Note:
  1. These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
Name: CxCON
Offset: 0x2600, 0x28F0

Bit 3130292827262524 
 TXBWS[3:0]ABATREQOP[2:0] 
Access R/WR/WR/WR/WS/HCR/WR/WR/W 
Reset 00000100 
Bit 2322212019181716 
 OPMOD[2:0]TXQENSTEFSERR2LOMESIGMRTXAT 
Access RRRR/WR/WR/WR/WR/W 
Reset 10011000 
Bit 15141312111098 
 ON SIDLBRSDISBUSYWFT[1:0]WAKFIL 
Access R/WR/WR/WRR/WR/WR/W 
Reset 0000111 
Bit 76543210 
 CLKSELPXEDISISOCRCENDNCNT[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01100000 

Bits 31:28 – TXBWS[3:0] Transmit Bandwidth Sharing bits

Delay between two consecutive transmissions (in arbitration bit times)
ValueDescription
1111-1100 4096
1011 2048
1010 1024
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
0001 2
0000 No delay

Bit 27 – ABAT Abort All Pending Transmissions bit

ValueDescription
1 Signals all transmit buffers to abort transmission.
0 Module will clear this bit when all transmissions are aborted.

Bits 26:24 – REQOP[2:0] Request Operation Mode bits

ValueDescription
111 Sets Restricted Operation mode.
110 Sets Normal CAN 2.0 mode; error frames on CAN FD frames.
101 Sets External Loopback mode.
100 Sets Configuration mode.
011 Sets Listen Only mode.
010 Sets Internal Loopback mode.
001 Sets Disable mode.
000 Sets Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames.

Bits 23:21 – OPMOD[2:0] Operation Mode Status bits

ValueDescription
111 Module is in Restricted Operation mode.
110 Module is in Normal CAN 2.0 mode; error frames on CAN FD frames.
101 Module is in External Loopback mode.
100 Module is in Configuration mode.
011 Module is in Listen Only mode.
010 Module is in Internal Loopback .
001 Module is in Disable mode.
000 Module is in Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames.

Bit 20 – TXQEN  Enable Transmit Queue bit(1)

ValueDescription
1 Enables TXQ and reserves space in RAM.
0 Does not reserve space in RAM for TXQ.

Bit 19 – STEF  Store in Transmit Event FIFO bit(1)

ValueDescription
1 Saves transmitted messages in TEF.
0 Does not save transmitted messages in TEF.

Bit 18 – SERR2LOM  Transition to Listen Only Mode on System Error bit(1)

ValueDescription
1 Transitions to Listen Only mode on System Error.
0 Transitions to Restricted Operation mode on System Error.

Bit 17 – ESIGM  Transmit ESI in Gateway Mode bit(1)

ValueDescription
1 ESI is transmitted as recessive when the ESI of message is high or CAN controller is error passive.
0 ESI reflects error status of the CAN controller.

Bit 16 – RTXAT  Restrict Retransmission Attempts bit(1)

ValueDescription
1 Restricted retransmissions attempts, uses TXAT[1:0].
0 Unlimited number of retransmission attempts, TXAT[1:0] bits will be ignored.

Bit 15 – ON CAN Enable bit

ValueDescription
1 CAN module is enabled.
0 CAN module is disabled.

Bit 13 – SIDL CAN stop in Idle Mode bit

ValueDescription
1 Stops module operation in Idle mode.
0 Does not stop module operation in Idle mode.

Bit 12 – BRSDIS Bit Rate Switching (BRS) Disable bit

ValueDescription
1 Bit rate switching is disabled, regardless of BRS in the transmit message object.
0 Bit rate switching depends on the BRS of the transmit message object.

Bit 11 – BUSY CAN Module is Busy bit

ValueDescription
1 The CAN module is active.
0 The CAN module is inactive.

Bits 10:9 – WFT[1:0] Selectable Wake-up Filter Time bits

ValueDescription
11 T11 Filter
10 T10 Filter
01 T01 Filter
00 T00 Filter

Bit 8 – WAKFIL  Enable CAN Bus Line Wake-up Filter bit(1)

ValueDescription
1 Uses CAN bus line filter for wake-up.
0 CAN bus line filter is not used for wake-up.

Bit 7 – CLKSEL  CAN Module Clock Source Select bit(1)

ValueDescription
1 CAN module runs at system (CPU) clock.
0 CAN module clock is derived from Clock Generator 10.

Bit 6 – PXEDIS  Protocol Exception Event Detection Disabled bit(1)

A recessive “reserved bit” following a recessive FDF bit is called a “Protocol Exception”.
ValueDescription
1 Protocol exception is treated as a form error.
0 If a protocol exception is detected, CAN will enter the Bus Integrating state.

Bit 5 – ISOCRCEN  Enable ISO CRC in CAN FD Frames bit(1)

ValueDescription
1 Includes stuff bit count in CRC field and uses nonzero CRC initialization vector.
0 Does not include stuff bit count in CRC field and uses CRC initialization vector with all zeroes.

Bits 4:0 – DNCNT[4:0]  DeviceNet Filter Bit Number bits

ValueDescription
11111-10011 Invalid selection (compares up to 18 bits of data with EIDx)
10010 Compares up to Data Byte 2, bit 6 with EID17.
10001 Compares up to Data byte 2, bit 7 with EID16.
... ...
00010 Compares up to Data byte 0 bit 6 with EID1.
00001 Compares up to Data byte 0 bit 7 with EID0.
00000 Does not compare data bytes.