14.4.9 CAN Receive Interrupt Status Register
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxRXIFT: Accesses the top byte RXIF[31:24].
- CxRXIFU: Accesses the upper byte RXIF[23:16].
- CxRXIF: Accesses the byte RXIF[15:8].
- RFIFx is the ‘or’ of all enabled RX FIFO flags (individual flags need to be cleared in the FIFO register).
| Name: | CxRXIF |
| Offset: | 0x2620, 0x2910 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RFIF[30:23] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RFIF[22:15] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RFIF[14:7] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RFIF[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 31:1 – RFIF[30:0] Receive FIFO Interrupt Pending bits
| Value | Description |
|---|---|
| 1 | One or more enabled receive FIFO interrupts are pending for the respective FIFO. |
| 0 | No enabled receive FIFO interrupts for the respective FIFO are pending. |