14.4.22 CAN Transmit Queue Status Register

Note:
  1. The individual bytes in this multibyte register can be accessed with the following register names:
    • CxTXQSTAT: Accesses the top byte TXQSTA[31:24].
    • CxTXQSTAU: Accesses the upper byte TXQSTA[23:16].
    • CxTXQSTA: Accesses the byte TXQSTA[31:0].
  2. The TXQCI[4:0] bits give a zero-indexed value to the message in the TXQ. IF the TXQ is four messages deep (FSIZE = 3), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ.
  3. These bits are updated when a message completes (or aborts) or when the TXQ is reset.
Name: CxTXQSTA
Offset: 0x2654, 0x2944

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    TXQCI[4:0] 
Access RRRRR 
Reset 00000 
Bit 76543210 
 TXABTTXLARBTXERRTXATIF TXQEIF TXQNIF 
Access RRRHS/CRR 
Reset 000011 

Bits 12:8 – TXQCI[4:0]  Transmit Queue Message Index bits(2)

A read of this register will return an index to the message the FIFO will next attempt to transmit.

Bit 7 – TXABT  Message Aborted Status bit(3)

ValueDescription
1 Message was aborted.
0 Message completed successfully.

Bit 6 – TXLARB  Message Lost Arbitration Status bit(3)

ValueDescription
1 Message lost arbitration while being sent.
0 Message did not lose arbitration while being sent.

Bit 5 – TXERR  Error Detected During Transmission bit(3)

ValueDescription
1 A bus error occurred while the message was being sent.
0 A bus error did not occur while the message was being sent.

Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending bit

ValueDescription
1 Interrupt is pending.
0 Interrupt is not pending.

Bit 2 – TXQEIF Transmit Queue Empty Interrupt Flag bit

ValueDescription
1 TXQ is empty.
0 TXQ is not empty, at least one message is queued to be transmitted.

Bit 0 – TXQNIF Transmit Queue Not Full Interrupt Flag bit

ValueDescription
1 TXQ is not full.
0 TXQ is full.