14.4.36 CAN 2 Filter Control Register 0
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxFLTCON0T: Accesses the top byte FLTCON0[31:24].
- CxFLTCON0U: Accesses the upper byte FLTCON0[23:16].
- CxFLTCON0: Accesses the byte FLTCON0[31:0].
| Name: | C2FLTCON0 |
| Offset: | 0x29A0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLTEN3 | F3BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTEN2 | F2BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTEN1 | F1BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN0 | F0BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 31 – FLTEN3 Enable Filter 3 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 28:24 – F3BP[4:0] Pointer to FIFO when Filter 3 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 23 – FLTEN2 Enable Filter 2 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 20:16 – F2BP[4:0] Pointer to FIFO when Filter 2 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 15 – FLTEN1 Enable Filter 1 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 12:8 – F1BP[4:0] Pointer to FIFO when Filter 1 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 7 – FLTEN0 Enable Filter 0 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 4:0 – F0BP[4:0] Pointer to FIFO when Filter 0 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |