14.4.38 CAN 2 Filter Control Register 2
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxFLTCON2T: Accesses the top byte FLTCON2[31:24].
- CxFLTCON2U: Accesses the upper byte FLTCON2[23:16].
- CxFLTCON2: Accesses the byte FLTCON2[31:0].
| Name: | C2FLTCON2 |
| Offset: | 0x29A8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLTEN11 | F11BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTEN10 | F10BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTEN9 | F9BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN8 | F8BP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 31 – FLTEN11 Enable Filter 11 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 28:24 – F11BP[4:0] Pointer to FIFO when Filter 11 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 23 – FLTEN10 Enable Filter 10 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 20:16 – F10BP[4:0] Pointer to FIFO when Filter 10 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 15 – FLTEN9 Enable Filter 9 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 12:8 – F9BP[4:0] Pointer to FIFO when Filter 9 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |
Bit 7 – FLTEN8 Enable Filter 8 to Accept Messages bit
| Value | Description |
|---|---|
| 1 | Filter is enabled. |
| 0 | Filter is disabled. |
Bits 4:0 – F8BP[4:0] Pointer to FIFO when Filter 8 Hits bits
| Value | Description |
|---|---|
| 11111-00100 | Reserved |
| 00011 | Message matching filter is stored in FIFO 3. |
| 00010 | Message matching filter is stored in FIFO 2. |
| 00001 | Message matching filter is stored in FIFO 1. |
| 00000 | Reserved, FIFO 0 is the TX Queue and cannot receive messages. |