14.4.6 CAN Timestamp Control Register

Note:

The individual bytes in this multibyte register can be accessed with the following register names:
- CxTSCONT: Accesses the top byte TSCON[31:24].
- CxTSCONU: Accesses the upper byte TSCON[23:16].
- CxTSCON: Accesses the byte TSCON[31:0].

Name:	CxTSCON
Offset:	0x2614, 0x2904


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						TSRES	TSEOF	TBCEN
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
							TBCPRE[9:8]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	TBCPRE[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 18 – TSRES Timestamp Reset bit (CAN FD frames only)

Value	Description
1	Timestamp resets at sample point of the bit following the FDF bit.
0	Timestamp resets at sample point of Start-of-Frame (SOF).

Bit 17 – TSEOF Timestamp End-of-Frame bit (EOF)

Value	Description
1	Timestamp when frame is taken valid (11898-1 10.7): RX no error until last, but one bit of EOF TX no error until the end of EOF
0	Timestamp at “beginning” of frame: Classical Frame: At sample point of SOF FD Frame: see TSRES bit

Bit 16 – TBCEN Time Base Counter (TBC) Enable bit

Value	Description
1	Enables TBC.
0	Stops and resets TBC.

Bits 9:0 – TBCPRE[9:0] CAN Time Base Counter Prescaler bits

Value	Description
1111111111	TBC increments every 1024 clocks.
0000000000	TBC increments every 1 clock.

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