12.6.31 Auxiliary PWM Generator x Duty Cycle Adjustment Register
| Name: | APGxDCA |
| Offset: | 0x222, 0x258, 0x28E, 0x2C4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PGxDCA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – PGxDCA[7:0] APWM Generator x Duty Cycle Adjustment Value bits
Depending on the state of the selected PCI source, the APGxDCA value will be
added to the value in the APGxDC register to create the effective duty cycle. When
the PCI source is active, APGxDCA is added. When the PCI source is inactive, no
adjustment is made. Duty cycle adjustment is disabled when APGxDCA[7:0] =
0. The PCI source is selected using the DTCMPSEL bit.