12.6.13 Auxiliary PWM Generator x Control Register High
- The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0] bits if the PCI Sync function is enabled.
- The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local APWM Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be synchronized to the APWM Generator clock domain.
- APWM Generators are grouped into groups of four: APG1-APG4 and APG5-APG8, if available. Any generator within a group of four may be used to trigger another generator within the same group.
Legend: r = Reserved bit
| Name: | APGxCONH |
| Offset: | 0x1FE, 0x234, 0x26A, 0x2A0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MDCSEL | MPERSEL | MPHSEL | MSTEN | UPMOD[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | TRGMOD | SOCS[3:0] | |||||||
| Access | r | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – MDCSEL Main Duty Cycle Register Select bit
| Value | Description |
|---|---|
1 |
APWM Generator uses the AMDC register instead of APGxDC |
0 |
APWM Generator uses the APGxDC register |
Bit 14 – MPERSEL Main Period Register Select bit
| Value | Description |
|---|---|
1 |
APWM Generator uses the AMPER register instead of APGxPER |
0 |
APWM Generator uses the APGxPER register |
Bit 13 – MPHSEL Main Phase Register Select bit
| Value | Description |
|---|---|
1 |
APWM Generator uses the AMPHASE register instead of APGxPHASE |
0 |
APWM Generator uses the APGxPHASE register |
Bit 11 – MSTEN Main Update Enable bit
| Value | Description |
|---|---|
1 |
APWM Generator broadcasts software set/clear of the UPDATE status bit and EOC signal to other APWM Generators |
0 |
APWM Generator does not broadcast the UPDATE status bit state or EOC signal |
Bits 10:8 – UPMOD[2:0] APWM Buffer Update Mode Selection bits
| Value | Description |
|---|---|
| 011 |
Client Immediate Update: Updates data registers immediately, or as soon as possible, when a Main
update request is received. A Main update request will be transmitted if MSTEN
= |
| 010 |
Client SOC Update: Updates data registers at the start of the next cycle if a Main update
request is received. A Main update request will be transmitted if MSTEN =
|
| 001 |
Immediate Update: Updates data registers immediately, or as soon as possible, if UPDREQ =
|
| 000 | SOC
Update: Updates data registers at the start of the next PWM cycle
if UPDREQ = |
Bit 7 – Reserved
Maintain as ‘0’
Bit 6 – TRGMOD APWM Generator Trigger Mode Selection bit
| Value | Description |
|---|---|
1 |
APWM Generator operates in Retriggerable mode |
0 |
APWM Generator operates in Single Trigger mode |
Bits 3:0 – SOCS[3:0] Start-of-Cycle Selection bits(1,2,3)
| Value | Description |
|---|---|
1111 |
TRIG bit or PCI Sync function only (no hardware trigger source is selected) |
1110-0101 |
Reserved |
0100 |
APG4 trigger output selected by PGTRGSEL[2:0] (APG4EVT[2:0]) |
0011 |
APG3 trigger output selected by PGTRGSEL[2:0] (APG3EVT[2:0]) |
0010 |
APG2 trigger output selected by PGTRGSEL[2:0] (APG2EVT[2:0]) |
0001 |
APG1 trigger output selected by PGTRGSEL[2:0] (APG1EVT[2:0]) |
0000 |
Local EOC – APWM Generator is self-triggered |