12.6.17 Auxiliary APWM Generator x Event Register Low

Note:
  1. These events are derived from the internal PWM Generator time base comparison events.
Name: APGxEVTL
Offset: 0x206, 0x23C, 0x272, 0x2A8

Bit 15141312111098 
 ADTR1PS[4:0]ADTR1EN3ADTR1EN2ADTR1EN1 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
    UPDTRG[1:0]PGTRGSEL[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection bits

ValueDescription
11111

1:32

. . .
00010

1:3

00001

1:2

00000

1:1

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is APGxTRIGC Compare Event Enable bit

ValueDescription
1

APGxTRIGC register compare event is enabled as trigger source for ADC Trigger 1

0

APGxTRIGC register compare event is disabled as trigger source for ADC Trigger 1

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is APGxTRIGB Compare Event Enable bit

ValueDescription
1

APGxTRIGB register compare event is enabled as trigger source for ADC Trigger 1

0

APGxTRIGB register compare event is disabled as trigger source for ADC Trigger 1

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is APGxTRIGA Compare Event Enable bit

ValueDescription
1

APGxTRIGA register compare event is enabled as trigger source for ADC Trigger 1

0

APGxTRIGA register compare event is disabled as trigger source for ADC Trigger 1

Bits 4:3 – UPDTRG[1:0] Update Trigger Select bits

ValueDescription
11

A write of the APGxTRIGA register automatically sets the UPDATE bit

10

A write of the APGxPHASE register automatically sets the UPDATE bit

01

A write of the APGxDC register automatically sets the UPDATE bit

00

User must set the UPDREQ bit (APGxSTAT[3]) manually

Bits 2:0 – PGTRGSEL[2:0]  APWM Generator Trigger Output Selection bits(1)

ValueDescription
111

Reserved

110

Reserved

101

Reserved

100

Reserved

011

APGxTRIGC compare event is the APWM Generator trigger

010

APGxTRIGB compare event is the APWM Generator trigger

001

APGxTRIGA compare event is the APWM Generator trigger

000

EOC event is the APWM Generator trigger