12.6.40 Frequency Scale Register
| Name: | FSCL |
| Offset: | 0x302 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FSCL[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FSCL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – FSCL[15:0] Frequency Scale Register bits
The value in this register is added to the frequency scaling accumulator at each PWM host clock pulse. When the accumulated value exceeds the value of FSMINPER, a clock pulse is produced.