12.6.15 Auxiliary PWM Generator x I/O Control Register Low
| Name: | APGxIOCONL |
| Offset: | 0x202, 0x238, 0x26E, 0x2A4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLMOD | SWAP | OVRENH | OVRENL | OVRDAT[1:0] | OSYNC[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTDAT[1:0] | CLDAT[1:0] | FFDAT[1:0] | DBDAT[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – CLMOD Current Limit Mode Select bit
| Value | Description |
|---|---|
1 |
If PCI current limit is active, then the APWMxH and APWMxL output signals are inverted (bit flipping), and the CLDAT[1:0] bits are not used |
0 |
If PCI current limit is active, then the CLDAT[1:0] bits define the APWM output levels |
Bit 14 – SWAP Swap APWM Signals to APWMxH and APWMxL Device Pins bit
| Value | Description |
|---|---|
1 |
The APWMxH signal is connected to the APWMxL pin and the APWMxL signal is connected to the APWMxH pin |
0 |
APWMxH/L signals are mapped to their respective pins |
Bit 13 – OVRENH User Override Enable for APWMxH Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT1 provides data for output on the APWMxH pin |
0 |
APWM Generator provides data for the APWMxH pin |
Bit 12 – OVRENL User Override Enable for APWMxL Pin bit
| Value | Description |
|---|---|
1 |
OVRDAT0 provides data for output on the APWMxL pin |
0 |
APWM Generator provides data for the APWMxL pin |
Bits 11:10 – OVRDAT[1:0] Data for APWMxH/APWMxL Pins if Override is Enabled bits
If OVERENH = 1, then OVRDAT1 provides data for APWMxH.
If OVERENL = 1, then OVRDAT0 provides data for APWMxL.
Bits 9:8 – OSYNC[1:0] User Output Override Synchronization Control bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits occur when specified by the UPDMOD[2:0] bits in the APGxCONH register |
01 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits occur immediately (as soon as possible) |
00 |
User output overrides via the OVRENH/L and OVRDAT[1:0] bits are synchronized to the local APWM time base (next Start-of-Cycle) |
Bits 7:6 – FLTDAT[1:0] Data for APWMxH/APWMxL Pins if Fault Event is Active bits
If Fault is active, then FLTDAT1 provides data for APWMxH.
If Fault is active, then FLTDAT0 provides data for APWMxL.
Bits 5:4 – CLDAT[1:0] Data for APWMxH/APWMxL Pins if Current Limit Event is Active bits
If current limit is active, then CLDAT1 provides data for APWMxH.
If current limit is active, then CLDAT0 provides data for APWMxL.
Bits 3:2 – FFDAT[1:0] Data for APWMxH/APWMxL Pins if Feed-Forward Event is Active bits
If feed-forward is active, then FFDAT1 provides data for APWMxH.
If feed-forward is active, then FFDAT0 provides data for APWMxL.
Bits 1:0 – DBDAT[1:0]
Data for APWMxH/APWMxL Pins if Debug Mode is Active and FRZ =
1 bits
If Debug mode is active and FRZ = 1, then DBDAT1 provides data
for APWMxH and DBDAT0 provides data for APWMxL.
If Debug mode is active and FRZ = 0, the PWM outputs remain active. The PWM
PGx FRZ bits are controlled using MPLAB® IDE. To access the
peripheral FRZ bit, go to Project Properties and open the options for the debugger
being used (ICDx, for example). Select ‘Freeze Peripherals’ from the option
categories drop-down, then select the PWM PGx instance. By default, the FRZ bit is
set when Debug mode is entered.