12.6.11 Auxiliary PWM Event Output Control Register y

Note:

The event signal is stretched using the peripheral clock because different APGs may be operating from different clock sources. The leading edge of the event pulse is produced in the clock domain of the APWM Generator. The trailing edge of the stretched event pulse is produced in the peripheral clock domain.
No event will be produced if the selected APWM Generator is not present.
This is the APWM Generator output signal prior to Output mode logic and any output override logic.
This signal should be the APGx_clk domain signal prior to any synchronization into the system clock domain.
‘y’ denotes a common instance (A-F).

Name:	APWMEVTy(5)
Offset:	0x1F0, 0x1F2, 0x1F4, 0x1F6, 0x1F8, 0x1FA

Bit 15 – EVTyOEN APWM Event Output Enable bit

Value	Description
`1`	Event output signal is output on APWMEVTy pin
`0`	Event output signal is internal only

Value	Description
`1`	Event output signal is active-low
`0`	Event output signal is active-high

Value	Description
`1`	Event output signal pulse width is not stretched
`0`	Event output signal is stretched to eight APWM clock cycles minimum⁽¹⁾

Event output signal pulse will be two system clocks when this bit is set and EVTySTRD = 1.

Value	Description
`1`	Event output signal is synchronized to the system clock
`0`	Event output is not synchronized to the system clock

Value	Description
`1111`	High-resolution error event signal
`1110-1010`	Reserved
`1001`	ADC Trigger 2 signal
`1000`	ADC Trigger 1 signal
`0111`	STEER signal (available in Push-Pull Output modes only)⁽⁴⁾
`0110`	CAHALF signal (available in Center-Aligned modes only)⁽⁴⁾
`0101`	PCI Fault active output signal
`0100`	PCI current limit active output signal
`0011`	PCI feed-forward active output signal
`0010`	PCI Sync active output signal
`0001`	APWM Generator output signal⁽³⁾
`0000`	Source is selected by the PGTRGSEL[2:0] bits