12.6.12 Auxiliary PWM Generator x Control Register Low
- The APWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty cycle and period of the APWM Generator output.
Legend: r = Reserved bit
| Name: | APGxCONL |
| Offset: | 0x1FC, 0x232, 0x268, 0x29E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | TRGCNT[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HREN | CLKSEL[1:0] | MODSEL[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – ON Enable bit
| Value | Description |
|---|---|
1 |
APWM Generator is enabled |
0 |
APWM Generator is not enabled |
Bits 10:8 – TRGCNT[2:0] Trigger Count Select bits
| Value | Description |
|---|---|
111 |
APWM Generator produces eight PWM cycles after triggered |
110 |
APWM Generator produces seven PWM cycles after triggered |
101 |
APWM Generator produces six PWM cycles after triggered |
100 |
APWM Generator produces five PWM cycles after triggered |
011 |
APWM Generator produces four PWM cycles after triggered |
010 |
APWM Generator produces three PWM cycles after triggered |
001 |
APWM Generator produces two PWM cycles after triggered |
000 |
APWM Generator produces one PWM cycle after triggered |
Bit 7 – HREN APWM Generator x High-Resolution Enable bit
| Value | Description |
|---|---|
1 |
APWM Generator x operates in High-Resolution mode |
0 |
APWM Generator x operates in Standard Resolution mode |
Bits 4:3 – CLKSEL[1:0] Clock Selection bits
| Value | Description |
|---|---|
11 |
APWM Generator uses Host clock scaled by frequency scaling circuit(1) |
10 |
APWM Generator uses Host clock divided by clock divider circuit(1) |
01 |
APWM Generator uses Host clock selected by the MCLKSEL[1:0] (APCLKCON[1:0]) control bits |
00 |
No clock selected, APWM Generator is in the Lowest Power state (default) |
Bits 2:0 – MODSEL[2:0] Mode Selection bits
| Value | Description |
|---|---|
111 |
Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle) |
110 |
Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle) |
101 |
Double-Update Center-Aligned PWM mode |
100 |
Center-Aligned PWM mode |
011 |
Reserved |
010 |
Independent Edge PWM mode, dual output |
001 |
Variable Phase PWM mode |
000 |
Independent Edge PWM mode |