12.6.14 Auxiliary PWM Generator x Status Register

Note:

User software may write a ‘1’ to CAP as a request to initiate a software capture. The CAP status bit will be set when the capture event has occurred. No further captures will occur until CAP is cleared by software.

Legend: R = Readable bit; HS = Hardware Settable bit; C = Clearable bit

Name:	APGxSTAT
Offset:	0x200, 0x236, 0x26C, 0x2A2


Bit	15	14	13	12	11	10	9	8
	SEVT	FLTEVT	CLEVT	FFEVT	SACT	FLTACT	CLACT	FFACT
Access	R/HS/C	R/HS/C	R/HS/C	R/HS/C	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TRSET	TRCLR	CAP	UPDATE	UPDREQ	STEER	CAHALF	TRIG
Access	W	W	R/W/HS	R	W	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 15 – SEVT PCI Sync Event bit

Value	Description
`1`	A PCI Sync event has occurred (rising edge on PCI Sync output or PCI Sync output is high when module is enabled)
`0`	No PCI Sync event has occurred

Bit 14 – FLTEVT PCI Fault Active Status bit

Value	Description
`1`	A Fault event has occurred (rising edge on PCI Fault output or PCI Fault output is high when module is enabled)
`0`	No Fault event has occurred

Bit 13 – CLEVT PCI Current Limit Status bit

Value	Description
`1`	A PCI current limit event has occurred (rising edge on PCI current limit output or PCI current limit output is high when module is enabled)
`0`	No PCI current limit event has occurred

Bit 12 – FFEVT PCI Feed-Forward Active Status bit

Value	Description
`1`	A PCI feed-forward event has occurred (rising edge on PCI feed-forward output or PCI feed-forward output is high when module is enabled)
`0`	No PCI feed-forward event has occurred

Bit 11 – SACT PCI Sync Status bit

Value	Description
`1`	PCI Sync output is active
`0`	PCI Sync output is inactive

Bit 10 – FLTACT PCI Fault Active Status bit

Value	Description
`1`	PCI Fault output is active
`0`	PCI Fault output is inactive

Bit 9 – CLACT PCI Current Limit Status bit

Value	Description
`1`	PCI current limit output is active
`0`	PCI current limit output is inactive

Bit 8 – FFACT PCI Feed-Forward Active Status bit

Value	Description
`1`	PCI feed-forward output is active
`0`	PCI feed-forward output is inactive

Bit 7 – TRSET APWM Generator Software Trigger Set bit

User software writes a ‘1’ to this bit location to trigger an APWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘1’ when the APWM Generator is triggered.

Bit 6 – TRCLR APWM Generator Software Trigger Clear bit

User software writes a ‘1’ to this bit location to stop an APWM Generator cycle. The bit location always reads as ‘0’. The TRIG bit will indicate ‘0’ when the APWM Generator is not triggered.

Bit 5 – CAP Capture Status bit⁽¹⁾

Value	Description
`1`	APWM Generator time base value has been captured in APGxCAP
`0`	No capture has occurred

Bit 4 – UPDATE APWM Data Register Update Status/Control bit

Value	Description
`1`	APWM Data register update is pending – user Data registers are not writable
`0`	No APWM Data register update is pending

Bit 3 – UPDREQ APWM Data Register Update Request bit

User software writes a ‘1’ to this bit location to request an APWM Data register update. The bit location always reads as ‘0’. The UPDATE status bit will indicate ‘1’ when an update is pending.

Bit 2 – STEER Output Steering Status bit (Push-Pull Output mode only)

Value	Description
`1`	APWM Generator is in the 2nd cycle of Push-Pull mode.
`0`	APWM Generator is in the 1st cycle of Push-Pull mode.

Bit 1 – CAHALF Half Cycle Status bit (Center-Aligned modes only)

Value	Description
`1`	APWM Generator is in the 2nd half of the time base cycle
`0`	APWM Generator is in the 1st half of the time base cycle

Bit 0 – TRIG APWM Trigger Status bit

Value	Description
`1`	APWM Generator is triggered and APWM cycle is in progress
`0`	No APWM cycle is in progress