12.6.51 PWM Generator x Control Register High
- The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0] bits if the PCI Sync function is enabled.
- The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be synchronized to the PWM Generator clock domain.
- PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within a group of four may be used to trigger another generator within the same group.
Legend: r = Reserved bit
| Name: | PGxCONH |
| Offset: | 0x32C, 0x362, 0x398, 0x3CE, 0x43A, 0x4A6 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MDCSEL | MPERSEL | MPHSEL | MSTEN | UPMOD[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | TRGMOD | SOCS[3:0] | |||||||
| Access | r | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – MDCSEL Main Duty Cycle Register Select bit
| Value | Description |
|---|---|
1 |
PWM Generator uses the MDC register instead of PGxDC |
0 |
PWM Generator uses the PGxDC register |
Bit 14 – MPERSEL Main Period Register Select bit
| Value | Description |
|---|---|
1 |
PWM Generator uses the MPER register instead of PGxPER |
0 |
PWM Generator uses the PGxPER register |
Bit 13 – MPHSEL Main Phase Register Select bit
| Value | Description |
|---|---|
1 |
PWM Generator uses the MPHASE register instead of PGxPHASE |
0 |
PWM Generator uses the PGxPHASE register |
Bit 11 – MSTEN Main Update Enable bit
| Value | Description |
|---|---|
1 |
PWM Generator broadcasts software set/clear of the UPDATE status bit and EOC signal to other PWM Generators |
0 |
PWM Generator does not broadcast the UPDATE status bit state or EOC signal |
Bits 10:8 – UPMOD[2:0] PWM Buffer Update Mode Selection bits
| Value | Description |
|---|---|
| 011 |
Client Immediate Update: Updates data registers immediately, or as soon as possible, when a Main update request is
received. A Main update request will be transmitted if MSTEN =
|
| 010 | Client SOC
Update: Updates data registers at start of next cycle if a Main update
request is received. A Main update request will be transmitted if MSTEN =
|
| 001 | Immediate Update: Updates data registers
immediately, or as soon as possible, if UPDREQ = |
| 000 | SOC Update: Updates data registers at start
of next PWM cycle if UPDREQ = |
Bit 7 – Reserved
Maintain as ‘0’
Bit 6 – TRGMOD PWM Generator Trigger Mode Selection bit
| Value | Description |
|---|---|
1 |
PWM Generator operates in Retriggerable mode |
0 |
PWM Generator operates in Single Trigger mode |
Bits 3:0 – SOCS[3:0] Start-of-Cycle Selection bits(1,2,3)
| Value | Description |
|---|---|
| 1111 | TRIG bit or PCI Sync function only (no hardware trigger source is selected) |
| 1110-0101 | Reserved |
| 0100 |
PG4 or PG8 trigger output selected by PG4(8)EVT[2:0] (PGTRGSEL[2:0]) |
| 0011 |
PG3 or PG7 trigger output selected by PG3(7)EVT[2:0] (PGTRGSEL[2:0]) |
| 0010 |
PG2 or PG6 trigger output selected by PG2(6)EVT[2:0] (PGTRGSEL[2:0]) |
| 0001 |
PG1 or PG5 trigger output selected by PG1(5)EVT[2:0] (PGTRGSEL[2:0]) |
| 0000 | Local EOC - PWM Generator is self-triggered |