5.46 Read Status Register 1 (RDSR1), Read Status Register 2 (RDSR2), Read Status Register 3 (RDSR3)

The Read Status Register 1 (RDSR1), Read Status Register 2 (RDSR2) and Read Status Register 3 (RDSR3) commands output the contents of Status Register 1, Status Register 2 and Status Register 3, respectively. These commands are supported in both SPI and QPI modes. The status registers may be read at any time, including during a write operation. When a write operation is in progress, the BUSY bit in Status Register 1 should be polled before issuing any new commands to ensure that subsequent commands are correctly received by the device.

To read Status Register 1, 2, or 3, the host drives CE# low and issues the corresponding command in SPI or QPI mode: 05H for RDSR1, 35H for RDSR2, or 15H for RDSR3. The device then outputs the register data on the falling edge of the SCK signal. Data output continues until the operation is terminated by a low‑to‑high transition on CE#. See Figure 5-37 and Figure 5-38 for the instruction sequences in SPI and QPI modes, respectively.