5.20 DTR Fast Dual I/O Read (DTR_FDIOR)

The DTR Fast Dual I/O Read (DTR_FDIOR) instruction is initiated by issuing the 8-bit command BDH in SPI mode. After the command is accepted, the device switches to 2‑bit I/O operation with dual data rate to receive a 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. The clock cycles used for the mode configuration bits are included in the total dummy clock count. The number of dummy clocks depends on the operating frequency, as specified in Table 5-8. The appropriate dummy clock configuration must be programmed in Status Register 3, bits [1:0], prior to issuing this command. The CE# signal must remain active-low for the entire duration of the DTR Fast Dual I/O Read operation. Refer to Figure 5-19 for the detailed timing sequence.

After the dummy cycles, the device outputs data on SIO[1:0] using dual data rate, starting from the specified address. Data are continuously streamed across sequential addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments and, upon reaching the highest memory address, wraps around to the beginning of the address space.

The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle is another DTR Fast Dual I/O Read operation. When M[5:4] = [1:0], the device expects the next continuous instruction to be another BDH read command, and the opcode does not need to be reissued. In this mode, the host initiates the next DTR_FDIOR cycle by asserting CE# low and providing the 2‑bit wide input for the 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy cycles, data output begins from the specified address. There are no restrictions on accessible address locations.

When M[5:4] is set to any value other than [1:0], the device expects the next operation to be a new command instruction. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for twenty clock cycles, and then bring CE# high.