5.8 Instructions

Instructions are used to read, write and configure the MC25VF128 device. A complete list of instructions is provided in Table 5-11. All instructions, addresses and data are transferred with the most significant bit (MSb) first and the least significant bit (LSb) last.

Table 5-11. MC25VF128 Device Operation Instructions
Instruction	Description	Command Cycle⁽¹⁾	Interface		Address Cycles^(2,3)	Dummy Clocks	Data Cycles⁽³⁾	Max Frequency⁽⁴⁾
Instruction	Description	Command Cycle⁽¹⁾	SPI	QPI	Address Cycles^(2,3)	Dummy Clocks	Data Cycles⁽³⁾	Max Frequency⁽⁴⁾
Configuration
`RSTEN`	Reset Enable	66H	X	X	0	0	0	166 MHz
`RST`⁽⁵⁾	Reset Memory	99H	X	X	0	0	0	166 MHz
`EQIO`	Enable QIO	38H	X		0	0	0	166 MHz
`RSTQIO`	Reset QIO	FFH		X	0	0	0	166 MHz
Status Registers
`RDSR1`	Read Status Register 1	05H	X	X	0	0	1 to many	166 MHz
`RDSR2`	Read Status Register 2	35H	X	X	0	0	1 to many	166 MHz
`RDSR3`	Read Status Register 3	15H	X	X	0	0	1 to many	166 MHz
`WRSR1`⁽⁶⁾	Write Status Register 1	01H	X	X	0	0	1	166 MHz
`WRSR2`	Write Status Register 2	31H	X	X	0	0	1	166 MHz
`WRSR3`	Write Status Register 3	11H	X	X	0	0	1	166 MHz
`VSWREN`	Volatile Status Register Write Enable	50H	X	X	0	0	0	166 MHz
Identification
`RMDID`	Manufacturer Device ID	90H	X	X	3 (Address value of 000000H)	0	2	166 MHz
`RMDSDIO`⁽⁷⁾	Manufacturer Device ID SPI Dual IO	92H	X		3 (Address value of FFFFFFH)	4	2	166 MHz
`RMDQPIO`⁽⁸⁾	Manufacturer Device ID SPI Quad IO	94H	X		3 (Address value of 000000H)	6	2	166 MHz
`Jedec ID`	Jedec-ID Read	9FH	X	X	0	0	3	166 MHz
`SFDP`	Serial Flash Discoverable Parameters	5AH	X		3	8	1 to many	166 MHz
`RUID`	Read Unique ID	4BH	X		0	32	16	166 MHz
Read
`Read`	Read Memory	03H	X		3	0	1 to many	108 MHz
`High-Speed Read`	Read Memory at Higher Speed	0BH	X		3	8	1 to many	166 MHz
`High-Speed Read`	Read Memory at Higher Speed	0BH		X	3	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`FQIOR`	Fast Quad I/O Read	EBH	X		3⁽⁹⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`FQIOR`	Fast Quad I/O Read	EBH		X	3	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`WQIOR`	Word Quad I/O Read	E7H	X		3⁽⁹⁾	4/8 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`SDOR`	SPI Dual Output Read	3BH	X		3	8	1 to many⁽⁷⁾	166 MHz
`SDOIR`⁽¹⁰⁾	SPI Dual I/O Read	BBH	X		3	4/8 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`SQOR`	SPI Quad Output Read	6BH	X		3	8	1 to many⁽⁸⁾	166 MHz
`DTR_FR`	DTR Fast Read	0DH	X		3⁽¹²⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹²⁾	108 MHz
`DTR_FR`	DTR Fast Read	0DH		X	3⁽¹²⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹²⁾	108 MHz
`DTR_FDIOR`	DTR Fast Dual I/O Read	BDH	X		3⁽¹³⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹³⁾	108 MHz
`DTR_FQIOR`	DTR Fast Quad I/O Read	EDH	X		3⁽¹⁴⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹⁴⁾	108 MHz
`DTR_FQIOR`	DTR Fast Quad I/O Read			X	3⁽¹⁴⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹⁴⁾	108 MHz
`SB`	Set Burst with Wrap	77H	X		0	6	1⁽⁸⁾	166 MHz
`RBQPI`	Burst Read with Wrap in QPI	0CH		X	3	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`DTR_RBQPI`	DTR Burst Read with Wrap in QPI	0EH		X	3⁽¹⁴⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹⁴⁾	108 MHz
`SRP`	Set Read Parameters	C0H		X		0	1	166 MHz
Write Memory
`WREN`	Write Enable	06H	X	X	0	0	0	166 MHz
`WRDI`	Write Disable	04H	X	X	0	0	0	166 MHz
`SE` ⁽¹¹⁾	4-KB Sector Erase	20H	X	X	3	0	0	166 MHz
`BE_32KB⁽¹¹⁾`	32-KB Block Erase	52H	X	X	3	0	0	166 MHz
`BE_64KB⁽¹¹⁾`	64-KB Block Erase	D8H	X	X	3	0	0	166 MHz
`CE`	Chip Erase	60H or C7H	X	X	0	0	0	166 MHz
`PP`	Page Program	02H	X	X	3	0	1 to 256	166 MHz
`SPI Quad Inp.PP (1-1-4)`	SPI Quad Input Page Program	32H	X		3	0	1 to 256	166 MHz
Suspend/Resume
`SUS`	Program/Erase Suspend	75H	X	X	0	0	0	166 MHz
`RES`	Program/Erase Resume	7AH	X	X	0	0	0	166 MHz
Security ID
`RSR`	Read Security Register	48H	X		3	8	1 to 256	166 MHz
`PSR`	Program Security Register	42H	X		3	0	1 to 256 Bytes	166 MHz
`ESR`	Erase Security Register	44H	X		3	0	0	166 MHz
Power Saving
`PD`	Enter Power-Down Mode	B9H	X	X	0	0	0	166 MHz
`RPD`	Release from Power-Down and Read ID	ABH	X		0	0 or 24	0 or 1 to many	166 MHz
`RPD`	Release from Power-Down and Read ID	ABH		X	0	0 or 6	0 or 1 to many	166 MHz
Note: The command cycle is eight clock periods in SPI mode and two clock periods in QPI mode. Address bits above the most significant bit for each density may be set to either V_IL or V_IH. Address and data cycles operate with two clock periods in QPI mode and eight clock periods in SPI mode. Unless otherwise specified, the maximum operating frequency for all instructions is 166 MHz. The `RST` command is executed only if the `RSTEN` command is issued first. Any intervening command will disable the reset operation. The Write Status Register 1 command (01h) can be used to program both Status Register 1 and Status Register 2. Data cycles are four clock periods and operate on SIO[1:0]. Data cycles are two clock periods and operate on SIO[3:0]. The IOC bit must be set to `1` before issuing this command. Address cycles, mode bits and data cycles use two clock periods and operate on SIO[3:0]. The IOC bit must be set to `1` before issuing the command. Address cycles, mode bits and data cycles use four clock periods and operate on SIO[1:0]. Block Erase (64 KB) uses addresses AMS-A16; Block Erase (32 KB) uses addresses AMS-A15; Sector Erase (4 KB) uses addresses AMS-A12. The remaining addresses are “don’t care” and must be set to V_IL or V_IH. Address cycles are latched in on both the rising and falling edges of the clock, using one clock period in QPI mode and four clock periods in SPI mode. Data output also occurs on both clock edges, using one clock period in QPI mode and four clock periods in SPI mode. Address cycles are latched in on both the rising and falling edges of the clock, using two clock periods per address byte on SIO[1:0]. Data output also occurs on both clock edges, using two clock periods per data byte on SIO[1:0]. Address cycles are latched in on both the rising and falling edges of the clock, using one clock period per address byte on SIO[3:0]. Data output also occurs on both clock edges, using one clock period per data byte on SIO[3:0].