5.14 SPI Dual Output Read (SDOR)

The SPI Dual Output Read operation is initiated by issuing the 8-bit command (3BH), followed by three or four bytes and eight dummy clock cycles. CE# must remain active-low for the duration of the SPI Dual Output Read operation. See Figure 5-10 for the SPI Dual Output Read sequence.

Following the dummy clock cycles, the device outputs data on SIO[1:0], starting from the specified address. Data are continuously streamed through successive addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments after each data transfer. When the highest memory address is reached, the Address Pointer returns to the beginning of the address space.