5.17 Fast Quad I/O Read (FQIOR)
The Fast Quad I/O Read (FQIOR) instruction (EBH) requires the IOC bit in Status Register 2 to be set to 1 prior to execution. In SPI mode, the FQIOR operation is initiated by issuing the 8-bit command (EBH). After the command is received, the device switches to 4-bit I/O operation for three address bytes, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. The clock cycles used for mode configuration are included in the total dummy clock count. The number of dummy clock cycles depends on the operating frequency, as shown in Table 5-5. The appropriate dummy clock setting must be programmed in Status Register 3, bits [1:0], before issuing this command. CE# must remain active-low for the duration of the Fast Quad I/O Read operation. See Figure 5-14 for the Fast Quad I/O Read sequence.
After the dummy clock cycles, the device outputs data on SIO[3:0], starting from the specified address. Data are continuously streamed through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments and wraps to the beginning of the address space after the highest memory address is reached.
The Set Mode Configuration bits M[7:0] determine whether the next instruction cycle is another Fast Quad I/O Read command. When M[5:4] = [1:0], the device expects the next continuous instruction to be another EBH Read command and does not require the opcode to be re-entered. In this mode, the host may initiate the next FQIOR cycle by driving CE# low, sending three address bytes over the 4-bit bus, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy clocks, the device outputs data starting from the specified address. There are no restrictions on address location access in this mode.
When M[5:4] is set to any value other than [1:0], the device expects the next instruction initiated to be a new command. To exit or reset the Set Mode Configuration, the host drives CE# low, transmits FFH on SIO0 for eight clock cycles, and then drives CE# high. See Figure 5-15 for the SPI Quad I/O Mode Read sequence when M[5:4] = [1:0].
In QPI mode, the host initiates the operation by driving CE# low and issuing the Read command (0BH), followed by three address cycles and the Set Mode Configuration bits M[7:0]/dummy clocks defined by the Set Read Parameters instruction (C0H), as shown in Table 5-13. The number of dummy cycles depends on the operating frequency. See Figure 5-9 for the High-Speed Read sequence for QPI mode. After the dummy clock cycles, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, starting from the specified address.
The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle is another Fast Quad I/O Read command. When M[5:4] = [1:0], the device expects the next continuous instruction to be another EBH Read command and does not require the opcode to be re-entered. In this mode, the host can initiate the next FQIOR cycle by driving CE# low, transmitting three address bytes over the 4-bit bus, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy clocks, the device outputs data starting from the specified address. There are no restrictions on address location access.
When M[5:4] is set to any value other than [1:0], the device expects the next instruction to be a new command. To exit or reset the Set Mode Configuration, the host drives CE# low, transmits FFH on SIO0 for eight clock cycles, and then drives CE# high.