5.44 Program Security Register (PSR)

The Program Security Register (42H) instruction programs 1 to 256 bytes of data into a previously erased (FFH) Security Register 1, Security Register 2, or Security Register 3. The device ignores any Program Security Register instruction that targets an invalid or protected address (see Table 5-15). Before initiating a Program Security Register operation, the WREN instruction must be executed.

To perform the operation, the host drives CE# low, issues the PSR command (42H) in SPI mode, transmits three address bytes followed by the data bytes to be programmed, and then drives CE# high. The data length must be between 1 and 256 bytes, in whole‑byte increments.

If more than 256 bytes are transmitted, the device programs only the last 256 bytes received. If the target address does not begin at a page boundary and the amount of input data exceeds or overlaps the end of the page, the excess data wraps around and is programmed at the beginning of the same page.

Completion of the internally self‑timed program operation can be determined by polling the BUSY bit in Status Register 1 or by waiting for the specified T_PSR duration.