5.18 Word Quad I/O Read (WQIOR)

The Word Quad I/O Read (WQIOR) instruction (E7H) requires the IOC bit in Status Register 2 to be set to 1 before the command is executed. The WQIOR operation is initiated by issuing the 8-bit E7H command in SPI mode. After the command is accepted, the device switches to 4‑bit I/O mode to receive a 3‑byte address. For this command, address bit A0 must be set to 0. The address phase is followed by the Set Mode Configuration bits M[7:0]/dummy clocks. The number of dummy clocks depends on the operating frequency, as specified in Table 5-8. The appropriate dummy clock configuration must be programmed in Status Register 3, bits [1:0], prior to issuing the WQIOR command. The CE# signal must remain active-low for the duration of the Word Quad I/O Read operation. Refer to Figure 5-16 for the detailed WQIOR timing sequence.

After the dummy cycles, the device outputs data on SIO[3:0], starting from the specified address. Data are continuously streamed across sequential addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments and, upon reaching the highest memory address, wraps around to the beginning of the address space.

The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle is another Word Quad I/O Read operation. When M[5:4] = [1:0], the device expects the next continuous instruction to be another Read command, and the opcode does not need to be reissued. In this mode, the host initiates the next WQIOR cycle by asserting CE# low and providing the 4‑bit wide input for the 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy clocks, data output begins from the specified address. There are no restrictions on accessible address locations.

When M[5:4] is set to any value other than [1:0], the device expects the next operation to be a new command instruction. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for eight clock cycles, and then deassert CE# high.