5.21 DTR Fast Quad I/O Read (DTR_FQIOR)
The DTR Fast Quad I/O Read (DTR_FQIOR) instruction EDH requires the IOC bit in Status Register 2 to be set to 1 before the command is executed. The operation is initiated by issuing the 8-bit EDH command EDH in SPI mode. After the command is received, the device switches to 4‑bit I/O operation with dual data rate to accept a 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. The clock cycles used for the mode configuration bits are included in the total dummy clock count. The number of dummy clocks depends on the operating frequency, as specified in Table 5-8. The appropriate dummy clock configuration must be programmed in Status Register 3, bits [1:0], prior to issuing the command. The CE# signal must remain asserted low for the entire duration of the DTR Fast Quad I/O Read operation. Refer to Figure 5-20 for the detailed timing sequence.
After the dummy cycles, the device outputs data on SIO[3:0] using dual data rate, starting from the specified address. Data are continuously streamed across sequential addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments and, upon reaching the highest memory address, wraps around to the beginning of the address space.
The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle is another DTR Fast Quad I/O Read operation. When M[5:4] = [1:0], the device expects the next continuous instruction to be another EDH read command, and the opcode does not need to be reissued. In this mode, the host initiates the next DTR_FQIOR cycle by asserting CE# low and providing the 4‑bit wide input for the 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy cycles, data output begins from the specified address. There are no restrictions on accessible address locations.
When M[5:4] is set to any value other than [1:0], the device expects the next operation to be a new command instruction. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for ten clock cycles, and then deassert CE# high. Refer to Figure 5-15 for the DTR Fast Quad I/O Read sequence when M[5:4] = [1:0].
In QPI mode, the host initiates the operation by asserting CE# low and issuing the Read command (EDH). The device then switches to 4‑bit I/O operation with dual data rate to receive the 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks defined by the Set Read Parameters (C0H) instruction, as described in Table 5-13. The required number of dummy clocks varies with the operating frequency. Refer to Figure 5-21 for the QPI mode timing sequence. After the dummy cycles, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, starting from the specified address.
The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle is another Fast Quad I/O Read operation. When M[5:4] = [1:0], the device expects the next continuous instruction to be another Read command (EDH), and the opcode does not need to be reissued. In this mode, the host initiates the next FQIOR cycle by asserting CE# low and providing the 4‑bit wide input for the 3‑byte address, followed by the Set Mode Configuration bits M[7:0]/dummy clocks. After the dummy clocks, the device outputs data starting from the specified address location. There are no restrictions on address location access.
When M[5:4] is set to any value other than [1:0], the device expects the next operation to be a new command instruction. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for ten clock cycles, and then bring CE# high.