5.45 Erase Security Register (ESR)

The Erase Security Register (44H) instruction erases Security Register 1, Security Register 2 or Security Register 3. If the instruction targets an invalid or protected address, it is ignored (see Table 5-15). For this instruction, address bits A9 to A0 are “don’t care.” Before initiating an Erase Security Register operation, the WREN instruction must be executed.

The Erase Security Register operation is supported in SPI mode. To perform the operation, the host drives CE# low, issues the ESR command (44H) in SPI mode, transmits three address bytes corresponding to the target Security Register, and then drives CE# high. Completion of the internally self-timed erase operation can be determined by polling the BUSY bit in Status Register 1 or by waiting for the specified T_ESR duration.