5.47 Write Status Register 1 (WRSR1), Write Status Register 2 (WRSR2), Write Status Register 3 (WRSR3)
The Write Status Register 1 (WRSR1), Write Status Register 2 (WRSR2) and Write Status Register 3 (WRSR3) commands are used to write new volatile or nonvolatile values to Status Register 1, Status Register 2, and Status Register 3, respectively. These commands are supported in both SPI and QPI modes. The writable STATUS register bits are as follows: SRP0, SEC, TB, and BP[2:0] in Status Register 1; CMP, LB[3:1], IOC, and SRP1 in Status Register 2; HOLD/RST, DRV1, DRV0, DC1, and DC0 in Status Register 3. All other STATUS register bits are read-only and are not affected by the Write Status Register instruction. The LB[3:1] bits are nonvolatile OTP bits; once set to 1, they cannot be cleared to 0.
To write nonvolatile values to the STATUS registers, a WREN (06H) instruction must be executed before issuing a WRSR1, WRSR2, or WRSR3 command. After the command is issued, completion of the internally self‑timed write operation can be determined by polling the BUSY bit in Status Register 1 or by waiting for the specified TWSR duration.
To write volatile values to the STATUS registers, a VSWREN (50H) instruction must be executed prior to issuing a WRSR1, WRSR2, or WRSR3 command. Volatile values are written within TCPH2 (30 ns). These values are lost upon power‑down or after a software or hardware reset, at which point the nonvolatile STATUS register values are restored.
To execute a WRSR1, WRSR2, or WRSR3 operation, the host drives CE# low, issues the corresponding command (01H)/(31H)/(11H) in SPI or QPI mode, followed by one data byte, and then drives CE# high. See Figure 5-39 and Figure 5-40 for the instruction sequence in SPI and QPI modes, respectively.
The IOC bit cannot be modified while the device is in QPI mode, as IOC must be set to 1 for the device to enter and remain in QPI mode.