5.13 High-Speed Read

The High-Speed Read instruction (0BH) is supported in both SPI and QPI modes. In SPI mode, the High-Speed Read operation is initiated by issuing the 8-bit command (0BH), followed by three address bytes and eight dummy clock cycles. See Figure 5-8 for the High-Speed Read sequence for SPI mode. After the dummy clock cycles, the device outputs data on SIO[1] on the falling edge of the SCK signal, starting from the specified address. Data are continually streamed through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each byte read. When the highest memory address is reached, the Address Pointer returns to address location 000000H.

In QPI mode, the host initiates the operation by driving CE# low and sending the Read command, 0BH, followed by three address cycles and a programmable number of dummy clock cycles. The required number of dummy clocks (4, 6, 8 or 10) is defined by the Set Read Parameters instruction (C0H) and varies based on the operating frequency. See Figure 5-9 for the High-Speed Read sequence for QPI mode. After the dummy clock cycles, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, starting from the specified address. Data are continuously streamed through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each data unit. When the highest memory address is reached, the Address Pointer returns to address location 000000H.