5.38 SPI Quad Input Page Program
The SPI Quad Input Page Program (32H) instruction programs up to 256 bytes of data into the memory. Before initiating this operation, the target page address must be in an erased state (FFH). If the instruction is applied to a protected memory region, it is ignored. This instruction requires the IOC bit in Status Register 2 to be set to 1 prior to execution. In addition, the Write Enable (WREN) instruction must be executed before issuing the SPI Quad Input Page Program command.
To perform the operation, the host drives CE# low, issues the SPI Quad Input Page Program command (32h), transmits three address bytes followed by the data to be programmed, and then drives CE# high. The amount of data programmed must be between 1 and 256 bytes, in whole‑byte increments. The command cycle is eight clock cycles long, while the address and data cycles are each two clock cycles long, with the most significant bit transmitted first. Completion of the internally self‑timed write operation can be determined by polling the BUSY bit in Status Register 1 or by waiting for the specified TPP duration. Refer to Figure 5-36 for the command sequence.
During a SPI Quad Input Page Program operation, the memory is organized into 256‑byte page boundaries. If more than 256 bytes are transmitted, the device programs only the last 256 bytes received. If the target address does not begin at a page boundary (A[7:0] are not all zero) and the data length exceeds the remaining bytes in the page, the excess data wraps around and is programmed at the beginning of the same page.